- 產品詳情
CPLD MAX? 系列 600 門 32 宏電池 0.8um 技術 5V 28 引腳窗口 CDIP
CY7C344具有28引腳，300 mil DIP或加窗j引腳陶瓷芯片載體(HLCC)，代表了該尺寸中密度最大的EPLD。8個專用輸入和16個雙向I/O引腳通信到一個邏輯陣列塊。在CY7C344 LAB中有32個宏細胞和64個膨脹產物項。當使用I/O宏單元格作為輸入時，使用兩個擴展器來創建輸入路徑。即使所有的I/O引腳都由宏單元寄存器驅動，仍然有16個“埋藏”寄存器可用。所有輸入、宏單元和I/O引腳在LAB內相互連接。
CY7C344的速度和密度使其成為所有類型應用的自然選擇。僅使用這一個器件，設計人員就可以實現復雜的狀態機、注冊邏輯和組合“粘合”邏輯，而無需使用多個芯片。這種架構靈活性允許CY7C344取代多芯片TTL解決方案，無論它們是同步的、異步的、組合的還是三者兼而有之。
特性
?高性能，高密度替代TTL，
74HC，以及自定義邏輯
?32個宏細胞，64個擴增產物項在一個LAB中
?8個專用輸入，16個I/O引腳
?0.8微米雙金屬CMOS EPROM技術
?28引腳，300 mil DIP, cerDIP或28引腳HLCC, PLCC封裝
Product Technical Specifications
| EU RoHS | Not Compliant |
| ECCN (US) | 3A001.a.2.c |
| Part Status | Obsolete |
| HTS | 8542.39.00.01 |
| Automotive | No |
| PPAP | No |
| Family Name | MAX? |
| Program Memory Type | EPROM |
| Number of Logic Blocks/Elements | 1 |
| Number of Macro Cells | 32 |
| Process Technology | 0.8um |
| Device System Gates | 600 |
| Data Gate | No |
| Maximum Number of User I/Os | 16 |
| Number of Flip Flops | 32 |
| In-System Programmability | No |
| Number of Inter Dielectric Layers | 2 |
| Programmability | Yes |
| Reprogrammability Support | No |
| Maximum Internal Frequency (MHz) | 62.5 |
| Maximum Clock to Output Delay (ns) | 15 |
| Maximum Propagation Delay Time (ns) | 25 |
| Speed Grade | 25 |
| Individual Output Enable Control | No |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Operating Current (mA) | 220 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Temperature Grade | Military |
| Tradename | MAX |
| Mounting | Through Hole |
| Package Height | 3.56(Max) |
| Package Width | 7.87(Max) |
| Package Length | 37.72(Max) |
| PCB changed | 28 |
| Standard Package Name | DIP |
| Supplier Package | Windowed CDIP |
| Pin Count | 28 |
| Lead Shape | Through Hole |
